The present invention relates to a matrix-type display and a repair method therefor, and more particularly, to a matrix-type display which can be repaired by pixel unit.
As an interface between a person and a computer, there are several flat panel displays such as liquid crystal displays (LCDs), plasma display panels (PDPs), electroluminesences (ELs) and field emission displays (FPDs), replacing conventional cathode ray tubes (CRTs). These flat panel displays adopt a matrix-type wiring layout in which horizontal and vertical signal lines cross.
This conventional matrix-type wiring layout is described with reference to the drawings.
FIG. 1 shows the layout of a conventional matrix-type display.
As shown in FIG. 1, in the conventional matrix-type display, a plurality of scanning lines G1, G2, . . . , and Gm are formed parallel to one another in the horizontal direction and a plurality of image signal lines D1, D2, D3, D4, . . . , D2n−1 and D2n are formed in the vertical direction, which cross the scanning lines with an insulating layer being interposed therebetween.
Each scanning line G1, G2, . . . , or Gm has an input pad GP1, GP2, . . . , GPm at one end through which scanning signals are input from outside, and each the image signal line D1, D2, D3, D4, . . . , D2n−1 or D2n also has input pads DP1, DP2, DP3, DP4, . . . , DP2n−1 and DP2n. Here, the input pads of a group of the image signal lines D1, D3, . . . and D2n−1 are formed at upper end of the data lines, and the other group of the image signal lines D2, D4, . . . and D2n have the input pads at their lower end.
On the other hand, pixels (PX) are formed in the region defined by the scanning lines G1, G2, . . . , Gm and the image signal lines D1, D2, D3, D4, . . . D2n−1 and D2n. Here, the layout of the pixels depend on the types of the displays.
The LCDs using an electro-optical effect of a liquid crystal materials have been highlighted among the flat panel displays. The driving modes of the LCD are roughly classified into a simple matrix type and an active matrix type.
The active matrix type LCD controls the pixels using a switching element having a non-linear characteristics. A thin film transistor (TFT) having three terminals is generally used as the switching element, and a thin film diode (TFD) such as a metal insulator metal (MIM) having two terminals is often used as the switching element.
Especially, the twisted nematic (TN) LCD adopting a TFT as a switching element is comprised of a TFT array panel, a color filter panel, and a liquid crystal material therebetween. The TFT array panel has TFTs, pixel electrodes, scanning lines (or gate lines) for transmitting scanning signals (or switching signals) and image signal lines or data lines for supplying a image signal. The color filter panel consists of a common electrode and color filters.
Hereinafter, the pixel layout of the TFT LCD will be described with reference to FIG. 2.
FIG. 2 shows a conventional TFT LCD. Each pixel (PX) includes a TFT, a liquid crystal capacitor Llc, a storage capacitor Cst, etc. The TFT is formed on a lower substrate, a liquid crystal capacitor Clc is comprised of a pixel electrode 10 on the lower substrate, a common electrode CE on an upper substrate and a liquid crystal material filled therebetween, and a storage capacitor Cst formed on the lower substrate. The storage capacitor Cst prevents the charges in the liquid crystal capacitor Clc from discharging for a time. On the other hand, the pixel PX is connected to a data line and a gate line via the TFT. For example, three terminals of the TFT are connected to the data line, the gate line and the pixel electrode 10, respectively. However, in FIG. 2, the TFT for switching a pixel PX exists outside the pixel PX, that is, a terminal of the TFT is connected to a pixel electrode 10 of the adjacent pixel so as to drive the adjacent pixel. A TFT for driving a pixel may be formed in the corresponding pixel.
When either a constant voltage or a periodical voltage is applied to the common electrode CE, and a voltage is applied to the pixel electrode 10 via the TFT, the display operation is performed by the electro-optical effect of the liquid crystal material composing the liquid crystal capacitor Clc.
Referring to FIGS. 3 and 4, the plan layout and the vertical layout of the TFT array panel of the LCD shown in FIGS. 1 and 2 will be described.
FIG. 3 shows the layout of the TFT array panel corresponding to the lower panel of the LCD shown in FIG. 2. The gate line is in the shape of a closed curve enclosing the pixel electrode. FIG. 4 is a sectional view of a portion cut along a line A—A in FIG. 3. In fact, the regions represented by PXi (i=1, 2, 3, 4) having rectangle-like shapes, correspond to the lower portion of a pixel. For convenience, the rectangle-like regions including the gate line and the data line are called as “pixels” or “pixel regions”. Also, let a group of pixels formed along the horizontal direction and a group of pixels formed along the vertical direction as “a pixel row” and “a pixel column”, respectively.
As shown in FIGS. 3 and 4, the upper and lower gate lines Gup and Gdown are formed on a transparent insulating substrate in the above and below of a pixel row. The lower gate line Gdown extends straight in the horizontal direction. The upper gate line Gup is comprised of a first horizontal portion Gh1 which is the longest portion thereof, a first vertical portion Gv1 extending downward from the end of the first horizontal portion Gh1, a second horizontal portion Gh2, extending in the horizontal direction from the end of the first vertical portion Gv1, and a second vertical portion Gv2 extending upward from the end of the second horizontal portion Gh2. This layout of the upper gate line Gup is repeated by pixel. Generally, the above dual layout of the gate line is called as a dual gate line layout.
The first horizontal portion Gh1 of the upper gate line Gup and the lower gate line Gdown or are connected by a left auxiliary gate line 1a, and the second vertical portion Gv2 of the upper gate line Gup is lengthened downward to form a right auxiliary gate line 1b reaching the lower gate line Gdown.
A data line D is vertically formed between each pixel column and crosses with the first horizontal portion Gh1 of the upper gate line Gup and the lower gate line Gdown via an gate insulating layer 4 (see FIG. 4).
The upper and lower gate lines Gup and Gdown and a pair of the left and the right auxiliary gate lines 1a and 1b form a closed curve and serve as a black matrix. Within the region defined by the closed curve, there is a pixel electrode 10 which is overlapped with the gate lines Gup and Gdown and the auxiliary gate lines 1a and 1b. And a gate insulating layer 4 (see FIG. 4) and a protection layer 9 (see FIG. 4) are interposed between the pixel electrode 10 and the gate lines Gup and Gdown and the auxiliary gate lines 1a and 1b. The overlapped portions plays as the storage capacitor Cst (see FIG. 2). This storage capacitor formed along a closed curve is called a “ring capacitor”. However, only the upper and lower gate lines Gup and Gdown and the auxiliary gate lines 1a and 1b forming the ring capacitor is often called a ring capacitor. Here, a ring capacitor means the latter.
It is preferable that the gate lines Gup and Gdown and the auxiliary gate lines 1a and 1b have the above described layout of a closed-curve shape surrounding the pixel electrode 10 since a gate signal can be transferred even if the part of the gate lines Gup and Gdown and the auxiliary gate lines 1a and 1b are disconnected.
In the meantime, a TFT is formed on the second vertical portion Gv2 of the upper gate line Gup, which will be described in detail with reference to FIGS. 3 and 4.
A part of the second vertical portion Gv2 serves as a gate electrode 2 of the TFT. When the gate lines Gup and Gdown are made of material which can be anodized, such as aluminum, they, except gate pads (not shown) electrically connecting the gate lines Gup and Gdown to the outside, are anodized in general. Thus, a gate oxide layer 3 which is anodized part of the gate lines exists on the gate electrode 2. A gate insulating layer 4 is formed on the whole surface of the gate oxide layer 3 excluding the gate pad.
A semiconductor layer 5 is formed covering the gate electrode 2 with the gate insulating layer 4 being interposed therebetween. The semiconductor layer 5 is also formed on the gate lines Gup and Gdown to prevent a short between the gate lines Gup and Gdown and a data line D. Generally, the semiconductor layer 5 is made of amorphous silicon or polysilicon.
A contact layer 6 for improving an ohmic contact between the semiconductor layer 5 and a metal of the data line D is formed on the semiconductor layer 5, which is generally made of n+ amorphous silicon doped with n impurities of a high concentration.
The source electrode 7, which is a branch of the data line D, and the drain electrode 8 separated from the source electrode 7 are formed on the contact layer 6. Since the source electrode 7 locates near a cross point between the upper gate line Gup and the data line D, the source electrode 7 may be overlapped with the first horizontal portion Gh1 of the upper gate line Gup of the next pixel, as shown in FIG. 3. One end of the drain electrode 8 opposites to the source electrode 7 with respect to the gate electrode 2, and the other end of the drain electrode 8 is connected to the pixel electrode 10 of the upper pixel in the same pixel column, with crossing the lower gate line Gdown or of the upper pixel. For example, as shown in FIG. 3, the drain electrode 8 of the pixel PX2 is connected to the pixel electrode 10 of the pixel PX1 which is the upper pixel of the same pixel column, with crossing the lower gate line Gdown located beneath the pixel electrode 10 of the pixel PX1.
A passivation layer 10 covers the resultant surface where the source electrode 7 and the drain electrode 8 are formed, excluding on the contact portion between the drain electrode 8 and the pixel electrode 10 and pads (not shown), and the pixel electrode 10 made of a transparent conductive material is formed on the passivation layer 9.
In the pixel layout shown in FIG. 3, a TFT (including a gate electrode, a source electrode and a drain electrode) formed in a pixel region does not drive the pixel electrode in the pixel region. However, for the convenience, the TFT will be called “the TFT (the gate electrode, the source electrode and the drain electrode) of the pixel” through the whole specification.
The described above, the flat panel displays, particularly, the TFT array panel for the LCD has wirings such as the gate and the data lines for supplying signals to the pixels. These wirings may be easily disconnected or shorted by a topographical characteristic of the region through which they pass or by the subsequent heat treatments or etching processes. If a wiring is disconnected or shorted, the signals required for driving the pixel cannot be applied and the display operation cannot be performed properly.
In fact, the above described LCD having the gate wiring layout including the upper and the lower gate lines Gup and Gdown and the auxiliary gate lines 1a and 1b, the disconnection of the gate wiring Gup, Gdown, 1a and 1b is easily repaired. However, in cases of the disconnection of the data line D, the short of the pixel electrode 10 and the gate wiring Gup, Gdown, 1a and 1b, and the defect of the gate electrode 2, it is difficult to repair.
To solve the above problems, several solutions have been suggested. Among the solutions, one solution uses a repair line formed in a shape of a closed curve around a display region comprised of the pixels. The repair line crosses the gate lines and the data lines with being overlapped with them via an insulating layer. If a wiring is disconnected, then the repair line complements the disconnected wiring.
The conventional matrix-type display in which a repair line is formed in shape of a closed curve around a display region will be described in detail with reference to FIG. 5.
As shown in FIG. 5, a repair line RL made of a conductive material crosses a plurality of linear scanning lines G1, G2, . . . , Gm formed in the horizontal direction and a plurality of linear image signal lines D1, D2, D3, D4, . . . , D2n−1 and D2n crossing the linear scanning lines. The repair line RL crosses once each scanning line G1, G2, . . . , or Gm, and twice each image signal line D1, D2, D3, D4, . . . , D2n−1 or D2n, at the upper and the lower end portions. Here, since the cross points of the repair line RL, the scanning lines G1, G2, . . . , Gm and the image signal lines D1, D2, D3, D4, . . . , D2n−1, and D2n have insulating layers therebetween, the cross portions play as capacitors.
Hereinafter, the operation of the above described matrix-type display will be described in detail.
Switching signals are applied to the TFTs in each pixel row in sequence via the scanning lines G1, G2, . . . , and Gm formed in the horizontal direction and image signals are applied to the pixel electrodes 10 via the image signal lines D1, D2, D3, D4, . . . , D2n−1 and D2n and the TFTs.
For example, as shown FIG. 5, supposing that an image signal line D3 is disconnected. The open point is represented as a mark “≈”. An image signal passing through the image signal line D3 does not reach a portion of the data line below the open point. Then, the upper and the lower cross points of the image signal line D3 and the repair line RL, represented by Δ, are shorted using a laser. Concerning a pixel connected to the image signal line D3 below the disconnect point, an image signal from the input pad DP3 passes the shorted upper cross point, moves along a left path P1 or a right path P2 of the repair line RL. However, since the right path P2 is longer than the path P1 and crosses more image signal lines than the path P1 cross, it is more effective to use the left path P1 than to use the path P2. Thus, it is required to transmit the signal only along the path P1 and to block the path P2. Therefore, two points on the path P2 represented by a mark “x”, which are near the short points, are cut. As a result, the signal can be applied to the image signal line D3 below the disconnect point via the path P1 of the repair line RL.
In the meantime, the signal passing through the path P1 is forced to meet the cross points a and a′ of the image signal lines D1 and D2 and the repair line RL. In fact, as described above, the cross points a and a′ function as a capacitor which distorts the image signal passing through the repair line RL. Particularly, since the number of the electrical lines increases, the number of the cross points existing on the path as the size of the screen increases, and thus the number of the capacitors increases, the overall electrostatic capacitance also increases and the signal distortion increases. In addition, since the length of the repair line RL increases and thus the resistance increases, the signal passing through the repair line RL is further distorted by a RC time delay.
Also, the number of the image signal lines D1, D2, D3, D4, . . . , D2n−1 and D2n which can be repaired using the repair line RL is limited due to the limitation of a space.
Furthermore, when pixel defects, such as disablement of transmission of the image signals to the pixel electrodes, are generated due to the defect of the TFTs, it is impossible to repair.